High-speed scrubbing demonstration using an optically reconfigurable gate array
نویسندگان
چکیده
منابع مشابه
Optically Reconfigurable Gate Array
Reconfigurable processors, like the Field Programmable Gate Arrays (FPGA's), open new computational paradigms where the processor is able to tailor its internal structure to better . implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully programmable by the user to perform a given application. By just changing its int...
متن کاملShield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array
To date, some types of Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize capabilities of rapid reconfiguration with numerous reconfiguration contexts. However, the layout style requires a shield against the reconfiguration light irradiation to guard transistors that constitute the gate array. This paper presents a shield effect for a circuit that is implemented on a ga...
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High-speed reconfigurable processors incorporating a reconfigurable memory and microprocessor array into a chip have been developed [1]. Such devices use a context-switching method. Their internal reconfigurable memory includes reconfiguration contexts of 16 banks. One bank includes a reconfiguration context used for ALUs that can be changed to others on a clock in nanoseconds. These devices ha...
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This paper introduces a new design of penternary inverter gate based on graphene nanoribbon field effect transistor (GNRFET). The penternary logic is one of Multiple-valued logic (MVL) circuits which are the best substitute for binary logic because of its low power-delay product (PDP) resulting from reduced complexity of interconnects and chip area. GNRFET is preferred over Si-MOSFET for circui...
متن کاملHSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array
This paper from the Berkeley BRASS group was all about performance: Is it possible to design an FPGA architecture that can compete with processors and ASICs in terms of clock frequency? FPGAs were (and still are) running at 5x – 10x slower clock frequency, largely due to the effect of configurability on both logic and interconnect delay. Von Herzen’s [1997] paper provided a sense of what was po...
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ژورنال
عنوان ژورنال: Optics Express
سال: 2017
ISSN: 1094-4087
DOI: 10.1364/oe.25.007807